Cirrus Logic EP93xx - Manual (Page 414)

10-20 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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During normal operation, using the “fair” rotating priority scheme shown in Table 10-2 , the last
channel to be serviced becomes the lowest priority channel with the others rotating
accordingly. In addition, any device requesting service is guaranteed to be recognized after
no more than eleven higher priority services has occurred. This prevents any one channel
from monopolizing the system. When the bus is idle, the scheme reverts to a fixed priority
whereby the highest priority request gets in first (as shown in
Table 10-2 ) when the bus
resumes to normal operation.
In the case where the two M2M channels are requesting a service, the [PW] size of the read
or write transfers for the first channel are completed before the read transfer for the second
channel begins. See subsections under
Section 10.1.5 for detailed information about
handshaking protocols for hardware and software-triggered M2M channel transfers.
10.2 Registers
10.2.1 DMA Controller Memory Map
Table 10-3 defines the DMA Controller mapping for each of 10 M2P (memory-to-peripheral)
channels (5 Tx and 5 Rx), plus the 2 M2M (memory-to-memory) channels.
Before programming a channel, the clock for that channel must be turned on by setting the
appropriate bit in the PwrCnt register of the Clock and State Controller block.
M2P Ch 7 M2P Ch 5
M2P Ch 8 M2P Ch 6
M2P Ch 9 M2P Ch 7
M2M Ch 0 M2P Ch 8
Lowest M2M Ch 1 M2P Ch 9
Table 10-3. DMA Memory Map
ARM920T Address Description Channel Base Address
0x8000_0000 -> 0x8000_003C M2P Channel 0 Registers (Tx) 0x8000_0000
0x8000_0040 -> 0x8000_007C M2P Channel 1 Registers (Rx) 0x8000_0040
0x8000_0080 -> 0x8000_00BC M2P Channel 2 Registers (Tx) 0x8000_0080
0x8000_00C0 -> 0x8000_00FC M2P Channel 3 Registers (Rx) 0x8000_00C0
0x8000_0100 -> 0x8000_013C M2M Channel 0 Registers 0x8000_0100
0x8000_0140 -> 0x8000_017C M2M Channel 1 Registers 0x8000_0140
0x8000_0180 -> 0x8000_01BC Not Used
0x8000_01C0 -> 0x8000_01FC Not Used
0x8000_0200 -> 0x8000_023C M2P Channel 5 Registers (Rx) 0x8000_0200
0x8000_0240 -> 0x8000_027C M2P Channel 4 Registers (Tx) 0x8000_0240
0x8000_0280 -> 0x8000_02BC M2P Channel 7 Registers (Rx) 0x8000_0280
0x8000_02C0 -> 0x8000_02FC M2P Channel 6 Registers (Tx) 0x8000_02C0
0x8000_0300 -> 0x8000_033C M2P Channel 9 Registers (Rx) 0x8000_0300
Table 10-2. M2P DMA Bus Arbitration (Continued)
Internal Arbitration Priority
CHARB = 0 CHARB = 1