Cirrus Logic EP93xx - Manual (Page 44)

2-6 DS785UM1
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
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2.2.3.3.2 Data Cache Enable
• A write to bit 2 of CP15 register 1 will enable or disable the Data Cache (D-Cache)/Write
Buffer
• The D-Cache may only be enabled when the MMU is enabled. All data accesses are
subject to MMU and permission checks
• If disabled, current contents are ignored. If re-enabled before a reset, contents will be
unchanged, but may not be coherent with external memory. Depending on system
software, a clean and invalidate action may be required before re-enabling.
2.2.3.3.3 Write Buffer Enable
• The Write Buffer is enabled via the page table entries in the MMU. The Write buffer
cannot be enabled unless the MMU is enabled.
2.2.4 Co-processor Interface
The MaverickCrunch co-processor is explained in detail in Chapter 3 on page 3-1 . The
relationship between the ARM co-processor instructions and MaverickCrunch co-processor
is also explained in
Chapter 3 .
The ARM co-processor instruction set includes:
• LDC - Load co-processor from memory
• STC - Store co-processor register from memory
• MRC - Move to ARM register from co-processor register
• MCR - Move to co-processor register from ARM register
The ARM co-processor has sixteen (C0 through C15) 64-bit registers for data transfer and
data manipulation. See
Chapter 3 , Section 3.2 on page 3-8 for a code example.
2.2.5 AMBA AHB Bus Interface Overview
The AHB (Advanced High-Performance Bus) is the high-performance system backbone bus.
Figure 2-2 on page 2-7 shows a typical AMBA AHB System.
The AHB connects devices that require high bandwidth, such as DMA controllers, external
memory, and co-processors. The AHB supports:
• Burst Transactions
• Split Transactions
• Bus Master hand-over to devices such as the MaverickCrunch co-processor or DMA
controller
• Single clock edge operations
The APB (Advanced Peripheral Bus) is a lower bandwidth, but lower power, bus that
provides: