Cirrus Logic EP93xx - Manual (Page 793)

DS785UM1 28-3
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
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28.1.1 Memory Map
The GPIO base address is 0x8084_0000. All registers are 8 bits wide and are aligned on
word boundaries. For all registers, the upper 24 bits are not modified when written and
always read zeros.
28.1.2 Functional Description
Each port has an 8-bit data register and an 8-bit direction register. The data direction register
controls whether each individual GPIO pin is an input or output. Writing to a data register only
affects the pins that are configured as outputs. Reading a data register returns the value on
the corresponding GPIO pins.
Ports A, B, and F also provide interrupt capability. The 16 interrupt sources from Ports A and
B are combined into a single signal GPIOINTR which is connected to the system interrupt
controller. All eight individual interrupt signals on Port F are available to the system interrupt
controller as GPIO0INTR through GPIO7INTR.
The interrupt properties of each of the GPIO pins on ports A, B, and F are individually
configurable. Each interrupt can be either high or low level sensitive or either positive or
negative edge triggered. It is also possible to enable debouncing on the Port A, B, and F
interrupts. Debouncing is implemented using a 2-bit shift register clocked by a 128 Hz clock.
There are seven additional registers for port A, B, and F:
• GPIO Interrupt Enable registers (GPIOAIntEn, GPIOBIntEn, GPIOFIntEn) control which
bits are to be configured as interrupts. Setting a bit in this register configures the
corresponding pin as an interrupt input.
• GPIO Interrupt Type 1 registers (GPIOAIntType1, GPIOBIntType1, GPIOFIntType1)
determines interrupt type. Setting a bit in this register configures the corresponding
interrupt as edge sensitive; clearing it makes it level sensitive.
• GPIO Interrupt Type 2 registers (GPIOAIntType2, GPIOBIntType2, GPIOFIntType2)
determines interrupt polarity. Setting a bit in this register configures the corresponding
interrupt as rising edge or high level sensitive; clearing it configures the interrupt as
falling edge or low level sensitive.
• GPIO End-Of-Interrupt registers (GPIOAEOI, GPIOBEOI, GPIOFEOI) are used to clear
specific bits in the interrupt Status Register. Writing a one to a bit will clear the
corresponding interrupt; writing a zero has no effect.
• GPIO Debounce registers (GPIOADB, GPIOBDB, GPIOFDB) enable debouncing of
specific interrupts signals.
• Interrupt Status registers (IntStsA, IntStsB, IntStsF) provide the status of any pending
unmasked interrupt.
• Raw Interrupt Status registers (RawIntStsA, RawIntStsB, RawIntStsF) provide the status
of any pending interrupt regardless of masking.