Cirrus Logic EP93xx - Manual (Page 603)

DS785UM1 17-7
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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The data word and flags are held in the 39-bit wide receiver FIFO. Reading an IrData word
removes both the data and its associated flag bits from the FIFO causing the next word in the
FIFO (if present) to be transferred into the IrFlag and data registers. However, all error
conditions encountered during a frame are remembered. At the end of frame they can be
read form the IrRIB register.
When a receive overrun (ROR) or FIR framing error (FRE) is detected the remainder of the
frame will be discarded by the receive logic (not put into the receive FIFO). In the case of
receive overruns, if the end of frame (EOF) bit in the last entry in the FIFO is clear then the
Receive Buffer Overrun (ROR) and EOF bits will be set. If an overrun occurs and the last
entry in the FIFO already has the EOF bit set then the RFL interrupt will be triggered. In the
case of a framing error an extra entry will be put into the FIFO with FIR Framing Error (FRE)
and EOF set, this entry will not contain any valid data.
If programmed IO is used to service the IrDA interface instead of DMA a similar process
occurs. Interrupt requests to service the receive FIFO will not occur until the rest of the frame
has been discarded.
At the end of a frame, a valid end of frame (EOF) or an abort (RAB), a DMA request
corresponding to the last word (which may hold 1, 2, 3, or 4 bytes of valid data) of the
received frame will be raised. DMA will take the word. At that point the receive FIFO should
be empty and the DMA request may be deasserted. The DMA request will be reasserted
when data for a following frame is loaded into the receive FIFO.
The above behavior means there is no need for ARM Core intervention to service the IrDA
interface between successive receive frames.
17.3.2.4 Special Conditions
17.3.2.4.1 Early Termination of Transmission
Clearing IrCon.TXE (transmit enable bit) stops transmission immediately. All data within the
FIFO, transmit buffer and serial output shifter is cleared.
17.3.2.4.2 Early Termination of Reception
Clearing IrCon.RXE receive enable bit stops reception immediately. All data within the
receive buffer, serial input shifter and FIFO is cleared.
17.3.2.4.3 Changing IrDA Mode
Poll the Transmitter Disabled bits – FD or MD bits – in IrEnable register until end of
transmission is indicated. The new mode can then be set as described in 4.2.1General
Configuration.
17.3.2.4.4 Loopback Mode
For test purposes, data will be looped back – internally – from the output of the transmit serial
shifter into the input of the receive serial shifter when IrEnable.LBM is set.