Cirrus Logic EP93xx - Manual (Page 791)

DS785UM1 28-1
Copyright 2007 Cirrus Logic
2
8
2
8
28
Chapter 28
28 GPIO Interface
28.1 Introduction
Note: The EP9301 and EP9302 processors each have 18 standard GPIOs and 19 enhanced
GPIOs.
Note: The EP9307 processor has 30 standard GPIOs and 18 enhanced GPIOs.
Note: The EP9312 processor has 31 standard GPIOs and 16 enhanced GPIOs.
Note: The EP9315 processor has 31 standard GPIOs and 24 enhanced GPIOs.
The General Purpose Input/Output (GPIO) is an Advanced Peripheral Bus (APB) slave
module. The GPIO block is the primary controller for the EGPIO, RDLED, GRLED, SLA[1:0],
EECLK, and EEDAT pins. It is a secondary controller for the ROW[7:0], COL[7:0], PCMCIA
and IDE control pins.
There are two types of GPIOs, standard and enhanced. The enhanced GPIO, called EGPIO,
have interrupt generation capability.
The GPIO block has eight ports, named Port A through Port H. Ports C, D, E, G, and H are
standard GPIO ports. Ports A, B, and F are enhanced GPIO ports.
Each GPIO port controls eight individual pins. Each port has an 8-bit data register and an 8-
bit data direction register. The EGPIO ports each have additional 8-bit registers for interrupt
configuration and status. The control of an individual pin is determined in a bit-slice fashion
across all registers for that port; only a single bit at a particular index from each register
affects or is affected by that pin.