Cirrus Logic EP93xx - Manual (Page 524)

14-2 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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The FIFOs can be programmed to be 1 byte deep providing a conventional double-buffered
UART interface.
The modem status input signals Clear To Send (CTS), Data Carrier Detect (DCD) and Data
Set Ready (DSR) are supported. The additional modem status input Ring Indicator (RI) is not
supported. Output modem control lines, such as Request To Send (RTS) and Data Terminal
Ready (DTR), are not explicitly supported. Note that the separate modem block described
later in this chapter does provide support for RI, RTS, and DTR.
14.2.1 UART Functional Description
A block diagram of the UART is shown in Figure 14-1 .
14.2.1.1 AMBA APB Interface
The AMBA APB interface generates read and write decodes for accesses to status and
control registers and transmit and receive FIFO memories.
The AMBA APB is a local secondary bus which provides a low-power extension to the higher
bandwidth Advanced High-performance Bus (AHB) within the AMBA system hierarchy. The
AMBA APB groups narrow-bus peripherals to avoid loading the system bus and provides an
interface using memory-mapped registers which are accessed under program control.
14.2.1.2 DMA Block
The DMA interface passes data between the UART FIFOs and an external DMA engine as
an alternative to AMBA APB accesses. (See
Chapter 10, , “DMA Controller” on page 10-1 for
additional details.) It may be configured to automatically move characters from the DMA
engine to the transmit FIFO and from the receive FIFO to the DMA engine. The DMA engine
may also indicate certain error conditions in the receive data to the DMA engine. Note that
the DMA interface only supports 8-bit accesses to the FIFOs; status information in the
receive FIFO is not passed to the DMA engine.
The UART1DMACtrl register controls the private interface between the DMA engine and the
UART. Setting bit TXDMAE enables the transmit channel, while setting bit RXDMAE enables
the receive channel. Setting bit DMAERR allows the UART to communicate certain error
conditions to the DMA engine via RxEnd on the DMA channel. These conditions include
receiving a break, a parity error, or a framing error. Note that configuration of the DMA
channels in the DMA engine is also required for DMA operation with the UART.
14.2.1.3 Register Block
The register block stores data written or to be read across the AMBA APB interface.