Cirrus Logic EP93xx - Manual (Page 773)

DS785UM1 27-3
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
2
7
2
7
27
Note: NI = Not supported at this time.
27.2.2 PIO Operations
For PIO operations, the Pin Interface unit handles all the operations. Register read and write
operations by the host are sufficient to operate the IDE interface in PIO mode for both non-
data and data transfer in both directions.
Most IDE controllers handle this automatically, but this IDE controller does not. The diagrams
are located in Information Technology AT Attachment with Packet Interface (ATA/ATAPI-5),
Section 10.2.2, Figure 44. See
"Preface" chapter, “Reference Documents” on page P-3 for
additional information.
Initial state: pins DIORn and DIOWn low.
For a Read operation.
1. Write out the register value.
2. Delay as follows, based on the PIO mode.
PIO Mode 0 - Delay for 70 ns
PIO Mode 1 - Delay for 50 ns.
PIO Mode 2 - Delay for 30 ns.
PIO Mode 3 - Delay for 30 ns
PIO Mode 4 - Delay for 25 ns
3. Bring DIORn high.
4. Based on the PIO mode, delay as follows before the next read or write can occur.
PIO Mode 0 - Delay for 290 ns.
PIO Mode 1 - Delay for 290 ns
PIO Mode 2 - Delay for 290 ns.
PIO Mode 3 - Delay for 80 ns
PIO Mode 4 - Delay for 70 ns
5. Bring DIORn low.
6. Read IDE Data in the register.
IORDY/
DDMARDYn/
DSTROBE
- 1
Negate to extend the host transfer cycle of any host read or
write access/
Flow control signal for Ultra DMA data-out burst/
Flow control signal for Ultra DMA data-in burst
IOCS16n NI 1 Device indicates it supports 16-bit I/O bus cycles
PDIAGn/
CBLIDn
NI 1
Asserted by device 1 to indicate to device 0 that it has finished
diagnostic/
Cable assembly type identifier
DD[15:0] - 16 16-bit data interface between controller and device
Table 27-1. IDE Host to IDE Interface Definition (Continued)
IDE Pin Type
No. of
Pins
Description