Cirrus Logic EP93xx - Manual (Page 530)

14-8 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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• If the FIFOs are disabled (have a depth of one location) and there is no data present in
the transmitters single location, the transmit FIFO is asserted HIGH. It is cleared by
performing a single write to the transmitter FIFO.
The transmit interrupt UARTTXINTR is not qualified with the UART Enable signal, which
allows operation in one of two ways. Data can be written to the transmit FIFO prior to
enabling the UART and the interrupts. Alternatively, the UART and interrupts can be enabled
so that data can be written to the transmit FIFO by an interrupt service routine.
This interrupt is connected to the system interrupt controller.
14.2.3.4 UARTRTINTR
The receive timeout interrupt is asserted when the receive FIFO is not empty and no further
data is received over a 32-bit period. The receive timeout interrupt is cleared when the FIFO
becomes empty through reading all the data (or by reading the holding register).
This interrupt is not independently connected to the system interrupt controller.
14.2.3.5 UARTINTR
The interrupts are also combined into a single output which is an OR function of the individual
masked sources. This output is connected to the system interrupt controller to provide
another level of masking on a individual peripheral basis. The combined UART interrupt is
asserted if any of the four individual interrupts above are asserted and enabled.
14.3 Modem
The modem hardware adds modem control signals RTSn, DTRn, and RI. Two modem
support registers provide a 16550 compatible modem control interface.
14.4 HDLC
The HDLC receiver handles framing, address matching, CRC checking, control-octet
transparency or bit-stuffing, and optionally passes the CRC to the CPU at the end of the
packet. The HDLC transmitter handles framing, CRC generation, and control-octet
transparency or bit-stuffing. The CPU must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data
streams.
When entering HDLC mode, always enable HDLC transmit and/or receive first by setting the
TXE and/or RXE bit in the UART1HDLCCtrl, and then enable the UART. When leaving HDLC
mode, disable the UART first, and then disable HDLC transmit and/or receive by clearing the
TXE and/or RXE bit. This insures that no bytes are sent by the UART transmitter without
proper HDLC framing, and that no bytes are received via the UART receiver without proper
HDLC decoding. In HDLC mode, the UART should be configured to use 8-bit characters and
no parity bit.