5 integer saturation arithmetic, 5 integer saturation arithmetic -4 – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
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A double precision value requires all 64 bits:
A 32-bit integer is stored in the lower 32 bits of a 64-bit register and sign-extended when
written, provided the UI bit in the DSPSC is clear:
Hence, 32-bit integers may be used directly in calculations with 64-bit integers, which are
stored as:
3.1.5 Integer Saturation Arithmetic
By default, the co-processor treats all 32-bit and 64-bit integers as signed values and
automatically saturates the results of most integer operations and all conversions from
floating-point to integer format. Instructions that may saturate their results are:
•
CFADD32 and CFADD64
•
CFSUB32 and CFSUB64
•
CFMUL32 and CFMUL64
•
CFMAC32 and CFMSC32
•
CFCVTS32 and CFCVTD32
•
CFTRUNCS32 and CFTRUNCD32
This behavior, however, can be altered by setting the UI bit and the ISAT bit in the DSPSC.
With the UI bit clear (the default), 32-bit and 64-bit integer operations are treated as signed
with respect to overflow and underflow detection and saturation as well as compare
operations. Setting the UI bit causes the MaverickCrunch co-processor to treat all 32-bit and
64-bit integer operations as unsigned with respect to overflow, underflow, saturation, and
comparison.
Opcode
63
62
52 51
0
Sign Exponent
Significand
Opcode
63
32
31
30
0
Sign Extension
Sign
Data
Opcode
63
62
0
Sign Data