1 registers, 1 registers -17 – Cirrus Logic EP93xx User Manual
Page 539
DS785UM1
14-17
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
1
4
1
4
14
14.1 Registers
UART Register Descriptions
UART1Data
Address:
0x808C_0000 - Read/Write
Default:
0x0000_0000
Definition:
UART Data Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
DATA:
UART Data: read for receive data, write for transmit data
For words to be transmitted:
• • if the FIFOs are enabled, data written to this location is pushed onto the transmit
FIFO
• if the FIFOs are not enabled, data is stored in the transmitter holding register (the
bottom word of the transmit FIFO). The write operation initiates transmission from
the UART. The data is prefixed with a start bit, appended with the appropriate parity
bit (if parity is enabled), and a stop bit. The resultant word is then transmitted.
For received words:
• if the FIFOs are enabled, the data byte is extracted, and a 3-bit status (break, frame
and parity) is pushed onto the 11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are stored in the receiving
holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from the UART1Data register
while the corresponding status information can be read by a successive read of the
UART1RXSts register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
DATA