1 4 bpp word layout, 1 4 bpp word layout -10 – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
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memory and the other register,
, is used for the destination memory. All
start and stop values described below apply for source and destination values.
The two registers operate in an identical fashion for source and destination. To see how they
operate requires looking at several tables that show the memory layout for pixels in the
various color modes.
8.5.2.1 4 BPP Word Layout
This 4 BPP mode example is somewhat difficult because the pixels are not in sequential
order. For a Block Copy where 8 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
shows that Pixel 0 starts at bit 4, Pixel 1
starts at bit 0, etc. The start pixel, P0, is in the word at address 0x0000 and has a beginning
bit position of 4. This makes 4 = 0x4 the value that is used for the SPEL field in the
register.
Let the starting SDRAM address of the destination image be 0x0020.
shows that
Pixel 0 starts at bit 20, Pixel 1 starts at bit 16, etc. The start pixel, P0, is in the word at address
0x0020 and has a beginning bit position of 20. This makes 20 = 0x14 the value that is used
for the SPEL field in the
register.
The end pixel, P7, is in the word at address 0x0024 and has a beginning bit position of 8. This
makes 8 = 0x8 the value that is used for the EPEL field in the
register.
Note:The word count for this example would be: 2 - 1 = 1 words, since P7 ends in the 2nd word.
So, WIDTH = 0x1 would be written to the
register.
Table 8-13. 4 BPP Memory Layout for Source Image
Address
31
28
27
24
23
20
19
16
15
12
11
8
7
4
3
0
0x0000
P6
P7
P4
P5
P2
P3
P0
P1
Table 8-14. 4 BPP Memory Layout for Destination Image
Address
31
28
27
24
23
20
19
16
15
12
11
8
7
4
3
0
0x0020
P2
P3
P0
P1
0x0024
P6
P7
P4
P5