Cirrus Logic EP93xx - Manual (Page 665)

DS785UM1 21-9
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
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1
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21
21.5 I
2
S Bit Clock Rate Generation
21.5.1 Example of the Bit Clock Generation.
For nBCG = 0 and BCR[1:0] = “10” the bit clock frequency is fixed at 64 times LRCK for word
lengths of 32 and 24 and at 32x LRCK for word lengths of 16. In the case of 24 and 32 bit
words, this 64x clock is then gating depending on the I
2
S controller word size. If the I
2
S
controller word size is 32, then all of the 64x clock pulses are passed. If the I
2
S controller
word size is 24, then the last 8 64x clock pulses are gated off in a LRCK cycle. For an I
2
S
controller word size of 16 than all of the 32x clock pulses are passed. This is shown in
Figure 21-2 .
For other values of nBCG and BCR, the register bit descriptions define the bit clock
operation.
Output Data Bit
Align to SCLK Edge
When SPOL=1 and
i2s_mstr_clk_cfg[3]=0, transition of
output data bit and LRCK align to falling
edge of SCLK
When SPOL=0 and
i2s_mstr_clk_cfg[3]=1, transition of
output data bit and LRCK align to rising
edge of SCLK;
The output data bit is always a half-
cycle later to the SCLK edge which
aligns to LRCK transition. If the
SCLK rising edge is configured to
align to the LRCK transition, then
output data is aligned to falling edge
of SCLK. If the SCLK falling edge
aligns to the LRCK transition, then
output data aligns to the SCLK rising
edge.
Table 21-5. Bit Clock Rate Generation
Word
Length
Bit Clock
Rate
(BCR[1:0])
not Bit Clock
Gating
(nBCG)
Actual bit clock rate with respect to
LRCK
16 00 0 or 1 32x
24 00 0 64x with last 8 cycles gated off in each word.
24 00 1 64x Note the last 8 cycles are not gated off.
32 00 0 or 1 64x
Ignored 01 Ignored Fixed at 32x
Ignored 10 Ignored Fixed at 64x
Ignored 11 Ignored Fixed at 128x
Table 21-4. I2SClkDiv SYSCON Register Effect on I 2 S Clock Generation (Continued)
Function ORIDE=1 ORIDE=0