Cirrus Logic EP93xx - Manual (Page 483)

DS785UM1 12-5
Copyright 2007 Cirrus Logic
Static Memory Controller
EP93xx User’s Guide
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If the bit-width of an internal device that generates a read or write request is larger than the
bit-width of the memory device in the target memory space, the SMC will perform multiple
successive read or write accesses to the external device. For example, if an internal device
generates a 16-bit read request to an 8-bit external memory device, the SMC will perform two
successive read accesses to the 8-bit external device. The 8-bit data from the 1st read is
stored within the SMC until the 8-bit data from the 2nd read arrives. The SMC then combines
the data from the 1st and 2nd 8-bit read to form the requested 16-bit read data. The bus that
connects the internal device to the SMC cannot be used for any other purpose until after the
requested 16-bit read data is latched into the internal device.
During a write cycle, four byte lane output signals on the DQMn[3:0] pins notify the external
memory device of which byte lanes it should accept data from. See
Figure 12-2 . For
example, when the SBC performs an upper half-word (16-bit) write to a 32-bit-wide external
memory (32-bit bus), the SMC would output DQMn[3:0] = ‘0011’ to notify the external
memory that it should accept write data only from the upper two bytes on the 32-bit bus, and
not accept data from the lower two bytes on the 32-bit bus. In other words, the upper two
bytes in the 32-bit-wide memory would be written and the lower two bytes would remain as
they are (unwritten).
Each memory bank can be specified to operate with either single read and write accesses or
with burst-of-four (page mode) read and write accesses. During burst-of-four accesses, the
A[3] and A[4] address bits are internally incremented, ‘00’ –> ‘01’ –> ‘10’ –> ‘11’, to access
four sequential words. When using burst-of-four accesses, the address of the first access
must be on a quad-word address boundary. Burst-of-four or non-burst accesses are specified
by the value written to the PME bit in a bank control (SMCBCRx) register.
Note: The external device must support burst-of-four accesses.
12.3 PCMCIA Interface (EP9315 Processor Only)
With external logic, the PCMCIA Interface supports a PC Card in Slot 0 at 0x4000_0000.
Table 12-1 shows the memory address ranges. Address, data, and control signals for
interfacing to a PC Card are shown in Table 12-2 .
Table 12-1. PCMCIA Address Memory Ranges
Memory Space Bit [27:26] Address Range
IO 00 0x4000_0000 - 0x43FF_FFFF
Undefined 01 0x4400_0000 - 0x47FF_FFFF
Attribute 10 0x4800_0000 - 0x4BFF_FFFF
Memory 11 0x4C00_0000 - 0x4FFF_FFFF
Table 12-2. PCMCIA Pin Usage
Pin Name
Alternate Use If
No Card
PCMCIA Signal Name Note:
MCRDn nPOE 1
MCWRn nPWE 1
IORDn nPIORD 1