Cirrus Logic EP93xx - Manual (Page 409)

DS785UM1 10-15
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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• For a software-triggered M2M transfer, a memory-write is initiated when the 16-byte data
bay has been filled (in the case where 16 or more bytes remain to be transferred) or
when it contains the appropriate number of bytes (equal to BCR register value if BCR is
less than 16). The DMA controller drives the DAR_BASEx onto the address bus. This
address can be any aligned byte address. The BCR register decrements by the
appropriate number of bytes. When BCR = 0 then the transfer is complete. If BCR is
greater than zero, another read/write transfer is initiated.
• For transfers involving external devices or SSP/IDE, the DMA memory-write phase is
initiated when the data bay contains the byte/half-word/word data, depending on PW
value, that is, peripheral width. The DMA will then drive the DAR_BASEx onto the
address bus and will set the AMBA HSIZE signal in accordance with the PW value.
Once the DMA has received confirmation that the write is done (from HREADY in case
of an internal memory write, or from the SMC acknowledge signal in case of an external
device write), a wait state counter is started. During the count, the hardware request line
is masked, in order to allow the related peripheral to de-assert its request. In the case of
CONTROL.TM = “01” and the external device (which is the destination for the data) is
FIFO-based, it is up to software to program the DAH bit correctly (Destination Address
Hold), so that on successive transfers to the peripheral, the DAR_CURRENTx value will
not increment, thus reflecting the FIFO-nature of the peripheral.
10.1.10.4 Data Transfer Termination
The DMA Controller terminates a memory-to-memory channel transfer under the following
conditions:
• For software-triggered transfers which use a single buffer, the transfer is terminated
when the BCR register of the active buffer has reached zero. The DONE status bit and
corresponding interrupt (if enabled) are set. In the case of double/multiple buffer
transfers, termination occurs when the BCR registers of both buffer descriptors has
reached zero. The DONE status bit and corresponding interrupt (if enabled) are set.
When the DONE interrupt is set the processor can then write a one to clear the interrupt
before reprogramming the DMA to carry out another M2M transfer.
• For hardware-triggered transfers involving SSP or IDE or external devices without
handshaking signals, the transfer is also terminated when the BCR register of the active
buffer has reached zero. The DONE status bit and corresponding interrupt (if enabled)
are set. When the DONE interrupt is set, the processor can then write a one to clear the
interrupt before reprogramming the DMA to carry out another external DMA transfer.
• For operations involving external devices using a single buffer, the transfer is terminated
on the first occurrence of DEOT being asserted by the device or the byte count expiring
for the active buffer. In the case of the DMA receiving a DEOT from the peripheral (which
is aligned to DREQ) the DMA knows that this is the final transfer to be performed. The
DONE status bit and corresponding interrupt (if enabled) are set. In the case of
double/multiple buffer transfers, termination occurs on either the occurrence of the DMA
receiving a DEOT from the device while it is transferring to/from the last buffer (that is,
no other buffer has been set up), or when the BCR registers of both buffer descriptors
has reached zero.