Cirrus Logic EP93xx - Manual (Page 341)

DS785UM1 9-39
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
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1. RxMiss - This bit indicates that the receive frames have been missed which may be the
result of insufficient bus bandwidth being available, or of a lack of receive descriptors, or
free receive status locations.
2. RxBuffers - This bit is a warning that the last free receive descriptor has been read by
the controller, and RXDEnq is now zero.In a system with a dynamic number of receive
buffers, this may be use as a trigger to allocate more buffers.
3. End of Chain - This bit is set when the last transmit descriptor has been read into the
controller (TXDEnq equal to zero). The controller may still be transmitting at this time
due to the local descriptor and data storage. This bit may be used as a signal to add
more transmit descriptors, if available.
4. TxLenErr - This signifies that the controller has processed a transmit frame that exceeds
the maximum allowable length. This may be caused by an internal error in the controller,
a data corruption in the transmit descriptors, or a Host programming error in the
descriptor queue. The error will cause the Transmit Descriptor Processor to halt. The
Host should perform the Transmit Restart Process detailed in
Section 9.2.5.5 .
5. TxUnderrun Halt - When the Halt on Underrun (BMCtl) is set and an underrun occurs,
the Transmit Descriptor Processor will halt. The underrun may be the result of
insufficient bus bandwidth available, or the lack of the next transmit descriptor. The Host
should perform the Transmit Restart Process detailed in
Section 9.2.5.5 .
9.2.5.5 Transmit Restart Process
Following a halt of the Transmit Descriptor Processor from a Halt on Underrun, TxLength
Error, or setting the TxDis (BMCtl), processing may be restarted from the same point in the
queues or from a different point. To start from the same point, the Host only needs to set
BMCtl.TxEn. To start from a different point the following steps should be taken:
1. Process any transmit status entries in the transmit status queue (up to TXStsQCurAdd).
2. Set TxChRes in BMCtl and wait for the bit to clear. This ensures that the reset is
complete.
3. Set the TXDQBAdd to the start of the descriptor queue.
4. Set TXDQBLen to the length of the descriptor queue.
5. Determine the point in the transmit descriptor where the controller should start
processing, and set the TXDQCurAdd to this address. This point may be from the frame
which caused the initial problem.
6. Set the TXStsQBAdd to the start of the status queue.
7. Set the TXStsQBLen to the length of the status queue.
8. Determine the point at which the controller should start writing status entries, and set the
TXStsQCurAdd to this address. This can be the start of the status queue, as all existing
status entries have been processed.
9. Set TxEn in BMCtl. This will cause the Transmit Descriptor Processor to reinitialize.