Freescale Semiconductor DSP56366 - Manual (Page 103)

HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 6-9
If HDM1 or HDM0 are set, the DMA mode is enabled, and the HOREQ signal is used to request DMA
transfers (the value of the HM1, HM0, HLEND and HDREQ bits in the ICR have no affect). When the
DMA mode is enabled, the HDM2 bit selects the direction of DMA transfers:
• setting HDM2 sets the direction of DMA transfer to be DSP to host and enables the HOREQ signal
to request data transfer.
• clearing HDM2 sets the direction of DMA transfer to be host to DSP and enables the HOREQ
signal to request data transfer.
The HACK input signal is used as a DMA transfer acknowledge input. If the DMA direction is from DSP
to host, the contents of the selected register are driven onto the host data bus when HACK is asserted. If
the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK
is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits, HDM[1:0]. Only the
data registers TXH, TXM, TXL and RXH, RXM, RXL can be accessed in DMA mode.The HDI08 data
register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with
the value in HDM[1:0]. The address counter substitutes for the address bits of the HDI08 during a DMA
transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the
host data bus, the address counter is incremented to the next register. When the address counter reaches
the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in
HDM[1:0]. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need
0 0 1 DMA Mode Data Output
Transfers Enabled.
(24-Bit words)
0 1 0 DMA Mode Data Output
Transfers Enabled.
(16-Bit words)
0 1 1 DMA Mode Data Output
Transfers Enabled.
(8-Bit words)
1 0 1 DMA Mode Data Input
Transfers Enabled.
(24-Bit words)
1 1 0 DMA Mode Data Input
Transfers Enabled.
(16-Bit words)
1 1 1 DMA Mode Data Input
Transfers Enabled.
(8-Bit words)
Table 6-5 HDM[2:0] Functionality (continued)
HDM Mode
2 1 0 Description ICR
INIT HDM1 HDM0 HF1 HF0 TREQ RREQ