3 host control register (hcr), 1 hcr host receive interrupt enable (hrie) bit 0, 2 hcr host transmit interrupt enable (htie) bit 1 – Freescale Semiconductor DSP56366 User Manual
Page 101: 3 hcr host command interrupt enable (hcie) bit 2, Host control register (hcr) -7, Hcr host receive interrupt enable (hrie) bit 0 -7, Hcr host transmit interrupt enable (htie) bit 1 -7, Hcr host command interrupt enable (hcie) bit 2 -7, Figure 6-2, Host control register (hcr) (x:$ffffc2) -7
HDI08 – DSP-Side Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
6-7
NOTE
When writing data to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by the operation are updated. If the programmer
reads any of those status bits within the next two cycles, the bit will not
reflect its current status. See the
DSP56300 Family Manual
, Freescale
publication DSP56300FM for further details.
6.5.3
Host Control Register (HCR)
The HCR is 16-bit read/write control register used by the DSP core to control the HDI08 operating mode.
The initialization values for the HCR bits are described in
Section 6.5.9, "DSP-Side Registers After
. The HCR bits are described in the following paragraphs.
6.5.3.1
HCR Host Receive Interrupt Enable (HRIE) Bit 0
The HRIE bit is used to enable the host receive data interrupt request. When the host receive data full
(HRDF) status bit in the host status register (HSR) is set, a host receive data interrupt request occurs if
HRIE is set. If HRIE is cleared, HRDF interrupts are disabled.
6.5.3.2
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The HTIE bit is used to enable the host transmit data empty interrupt request. When the host transmit data
empty (HTDE) status bit in the HSR is set, a host transmit data interrupt request occurs if HTIE is set. If
HTIE is cleared, HTDE interrupts are disabled.
6.5.3.3
HCR Host Command Interrupt Enable (HCIE) Bit 2
The HCIE bit is used to enable the host command interrupt request. When the host command pending
(HCP) status bit in the HSR is set, a host command interrupt request occurs if HCIE is set. If HCIE is
cleared, HCP interrupts are disabled. The interrupt address is determined by the host command vector
register (CVR).
NOTE
Host interrupt request priorities: If more than one interrupt request source is
asserted and enabled (e.g. HRDF=1, HCP=1, HRIE=1 and HCIE=1), the
HDI08 generates interrupt requests according to the following table:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HDM2 HMD1 HDM0
HF3
HF2
HCIE
HTIE
HRIE
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2)