Freescale Semiconductor DSP56366 - Manual (Page 219)

DAX Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 10-3
• Parity generator (PRTYG)
• Preamble generator
• Biphase encoder
• Clock multiplexer
• Control state machine
XADR, XADBUFA, XADBUFB and XADSR creates a FIFO-like data path. Channel A is written to
XADR and moves to XADBUFA. Then channel B is written to XADR, and when XADBUFB empties
XADR moves into it. XADBUFA moves to the shift register XADSR when XADSR has shifted out its last
bit. After channel A audio and non-audio data has been shifted out, XADBUFB moves into XADSR, and
channel B audio and non audio shift begins.
The frame non-audio data (stored in XNADR) is transferred to the XADSR (for channel A) and to the
XNADBUF registers (for channel B) at the beginning of a frame transmission. This is called an “upload.”
The DAX audio data register empty (XADE) flag is set when XADR and XADBUFA are empty, and, if
the audio data register empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core.
The interrupt handling routine then sends the non-audio data bits to XNADR and the next frame of audio
data to XADR (two subframes).
At the beginning of a frame transmission, one of the 8-bit channel A preambles (Z-preamble for the first
subframe in a block, or X-preamble otherwise) is generated in the preamble generator, and then shifted out
to the ADO pin in the first eight time slots. The preamble is generated in biphase mark format. The
twenty-four audio and three non-audio data bits in the XADSR are shifted out to the biphase encoder,
which shifts them out through the ADO pin in the biphase mark format in the next 54 time slots. The parity
generator calculates an even parity over the 27 bits of audio and non-audio data, and then outputs the result
through the biphase encoder to the ADO pin at the last two time slots. This is the end of the first (channel
A) subframe transmission.
The second subframe transmission (channel B) starts with the preamble generator generating the channel
B preamble (Y-preamble). At the same time, channel B audio and non-audio data is transferred to the
XADSR shift-register from the XADBUFB and XNADBUF registers. The generated Y-preamble is output
immediately after the channel A parity and is followed by the audio and non-audio data in the XADSR,
which is in turn followed by the calculated parity for channel B. This completes a frame transmission.
When the channel B parity is sent, the audio data for the next frame, stored in XADBUFA and the
non-audio data bits from the XNADR, are uploaded to XADSR.
10.4 DAX Programming Model
The programmer-accessible DAX registers are shown in Figure 10-2 . The registers are described in the
following subsections. The Interrupt Vector table for the DAX is shown in Table 10-1 . The internal
interrupt priority is shown in Table 10-2 .