Freescale Semiconductor DSP56366 - Manual (Page 29)

DSP56300 Core Functional Blocks
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 1-5
the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated
or rounded into the MSP. Rounding is performed if specified.
1.4.2 Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to address data
operands in memory and contains the registers used to generate the addresses. It implements four types of
arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel
with other chip resources to minimize address-generation overhead.
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of
register triplets, and each register triplet is composed of an address register, an offset register, and a
modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset
adder).
A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo
value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is
also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference
between them is that the carry propagates in opposite directions. Test logic determines which of the three
summed results of the full adders is output.
Each Address ALU can update one address register from its respective address register file during one
instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used
in the address register update calculation. The modifier value is decoded in the Address ALU.
1.4.3 Program Control Unit (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception
processing. The PCU implements a seven-stage pipeline and controls the different processing states of the
DSP56300 core. The PCU consists of the following three hardware blocks:
• Program decode controller (PDC)
• Program address generator (PAG)
• Program interrupt controller (PIC)
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary
for pipeline control. The PAG contains all the hardware needed for program address generation, system
stack, and loop control. The PIC arbitrates among all interrupt requests (internal interrupts, as well as the
five external requests: IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt
vector address.
PCU features include the following:
• Position independent code support
• Addressing modes optimized for DSP applications (including immediate offsets)
• On-chip instruction cache controller
• On-chip memory-expandable hardware stack