Freescale Semiconductor DSP56366 - Manual (Page 148)

SHI Programming Considerations
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-24 Freescale Semiconductor
the HREQ line between two SHI-equipped DSPs, one operating as an I
2
C master device and the other as
an I
2
C slave device, enables full hardware handshaking.
7.7.4.1 Receive Data in I
2
C Master Mode
A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set.
Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each
received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line if the HIDLE
control bit is cleared. Data is acknowledged bytewise, as required by the I
2
C bus protocol, and is
transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the
responsibility of the programmer to select the correct number of bytes in an I
2
C frame so that they fit in a
complete number of words. For this purpose, the slave device address byte does not count as part of the
data; therefore, it is treated separately.
If the I
2
C slave transmitter is acknowledged, it should transmit the next data byte. In order to terminate the
receive session, the programmer should set the HIDLE bit at the last required data word. As a result, the
last byte of the next received data word is not acknowledged, the slave transmitter releases the SDA line,
and the SHI generates the stop event and terminates the session.
In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the
HRNE status bit is set, the HRX FIFO contains valid data, which may be read by the DSP with either DSP
instructions or DMA transfers. When the HRX FIFO is full, the SHI suspends the serial clock just before
acknowledge. In this case, the clock is reactivated when the FIFO is read (the SHI gives an ACK = 0 and
proceeds receiving).
7.7.4.2 Transmit Data In I
2
C Master Mode
A transmit session is initiated if the R/W direction bit of the transmitted slave device address byte is
cleared. Following a transmit initiation, the IOSR is loaded from HTX (assuming HTX is not empty) and
its contents are shifted out, MSB-first, on the SDA line. Following each transmitted byte, the SHI
controller samples the SDA line at the ninth clock pulse, and inspects the ACK status. If the transmitted
byte was acknowledged (ACK=0), the SHI controller continues transmitting the next byte. However, if it
was not acknowledged (ACK=1), the HBER status bit is set to inform the DSP side that a bus error (or
overrun, or any other exception in the slave device) has occurred. Consequently, the I
2
C master device
generates a stop event and terminates the session.
HTX contents are transferred to the IOSR when the complete word (according to HM[1:0]) has been
shifted out. It is, therefore, the responsibility of the programmer to select the right number of bytes in an
I
2
C frame so that they fit in a complete number of words. Remember that for this purpose, the slave device
address byte does not count as part of the data.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited.
When the HTX transfers its valid data word to the IOSR, the HTDE status bit is set and the DSP may write
a new data word to HTX with either DSP instructions or DMA transfers. If both IOSR and HTX are empty,
the SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with the
transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate
the transmit session).