Freescale Semiconductor DSP56366 - Manual (Page 240)

Timer/Event Counter Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
11-10 Freescale Semiconductor
NOTE
The INV bit affects both the timer and GPIO modes of operation. To ensure
correct operation, this bit should be changed only when one or both of the
following conditions is true:
• The timer has been disabled by clearing the TE bit in the TCSR.
• The timer is in GPIO mode.
The INV bit does not affect the polarity of the prescaler source when TIO0 is used as input to the prescaler.
11.3.4.6 TCSR Timer Reload Mode (TRM) Bit 9
The TRM bit controls the counter preload operation.
In timer (0–3) and watchdog (9–10) modes, the counter is preloaded with the TLR value after the TE bit
is set and the first internal or external clock signal is received. If the TRM bit is set, the counter is reloaded
each time after it reaches the value contained by the TCR. In PWM mode (7), the counter is reloaded each
time counter overflow occurs. In measurement (4–5) modes, if the TRM and the TE bits are set, the counter
is preloaded with the TLR value on each appropriate edge of the input signal.
If the TRM bit is cleared, the counter operates as a free-running counter and is incremented on each
incoming event. The TRM bit is cleared by the hardware RESET signal or the software RESET instruction.
11.3.4.7 TCSR Direction (DIR) Bit 11
The DIR bit determines the behavior of the TIO0 signal when it is used as a GPIO pin. When the DIR bit
is set, the TIO0 signal is an output; when the DIR bit is cleared, the TIO0 signal is an input. The TIO0
signal can be used as a GPIO only when the TC[3:0] bits are all cleared. If any of the TC[3:0] bits are set,
then the GPIO mode is disabled and the DIR bit has no effect.
The DIR bit is cleared by the hardware RESET signal or the software RESET instruction.
This bit is not in use for timers 1 and 2. It should be left cleared.
11.3.4.8 TCSR Data Input (DI) Bit 12
The DI bit reflects the value of the TIO0 signal. If the INV bit is set, the value of the TIO0 signal is inverted
before it is written to the DI bit. If the INV bit is cleared, the value of the TIO0 signal is written directly
to the DI bit.
DI is cleared by the hardware RESET signal or the software RESET instruction.
11.3.4.9 TCSR Data Output (DO) Bit 13
The DO bit is the source of the TIO0 value when it is a data output signal. The TIO0 signal is data output
when the GPIO mode is enabled and DIR is set. A value written to the DO bit is written to the TIO0 signal.
If the INV bit is set, the value of the DO bit is inverted when written to the TIO0 signal. When the INV bit
is cleared, the value of the DO bit is written directly to the TIO0 signal. When GPIO mode is disabled,
writing the DO bit has no effect.