Freescale Semiconductor DSP56366 - Manual (Page 131)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-7
7.4.4.1 HSAR Reserved Bits—Bits 19, 17–0
These bits are reserved. They read as zero and should be written with zero for future compatibility.
7.4.4.2 HSAR I
2
C Slave Address (HA[6:3], HA1)—Bits 23–20,18
Part of the I
2
C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit
slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain
the HA[6:0] slave device address. The full 7-bit slave device address is compared to the received address
byte whenever an I
2
C master device initiates an I
2
C bus transfer. During hardware reset or software reset,
HA[6:3] = 1011 and HA1 is cleared; this results in a default slave device address of 1011[HA2]0[HA0].
7.4.5 SHI Clock Control Register (HCKR)—DSP Side
The HCKR is a 24-bit read/write register that controls SHI clock generator operation. The HCKR bits
should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR).
For proper SHI clock setup, please consult the datasheet. The programmer should not use the combination
HRS = 1 and HDM[7:0] = 00000000, since it may cause synchronization problems and improper operation
(it is an illegal combination).
The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which is set. The
HCKR is not affected by the stop state.
The HCKR bits are described in the following paragraphs.
7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
The Clock Phase (CPHA) bit controls the relationship between the data on the master-in-slave-out (MISO)
and master-out-slave-in (MOSI) pins and the clock produced or received at the SCK pin. The CPOL bit
determines the clock polarity (1 = active-high, 0 = active-low).
The clock phase and polarity should be identical for both the master and slave SPI devices. CPHA and
CPOL are functional only when the SHI operates in the SPI mode, and are ignored in the I
2
C mode. The
CPHA bit is set and the CPOL bit is cleared during hardware reset and software reset.
The programmer may select any of four combinations of serial clock (SCK) phase and polarity when
operating in the SPI mode (See Figure 7-6).