Freescale Semiconductor DSP56366 - Manual (Page 80)

Interrupt Priority Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
4-6 Freescale Semiconductor
4.4 Interrupt Priority Registers
There are two interrupt priority registers in the DSP56366:
1. IPR-C is dedicated for DSP56300 Core interrupt sources.
2. IPR-P is dedicated for DSP56366 peripheral interrupt sources.
The interrupt priority registers are shown in Figure 4-1 and Figure 4-2 . The Interrupt Priority Level bits
are defined in Table 4-4 . The interrupt vectors are shown in Table 4-6 and the interrupt priorities are shown
in Table 4-5 .
Mode 6 Same as Mode 5 except SHI interface operates in the I
2
C slave mode with HCKFR set to 1 and the 100ns filter
enabled.
Mode 7 Same as Mode 5 except SHI interface operates in the I
2
C slave mode with HCKFR set to 0.
Mode 8 The DSP starts fetching instructions beginning at address $008000. Memory accesses are performed using
SRAM memory access type with 31 wait states and no address attributes selected.
Mode 9 Reserved. Used for Burn-In testing.
Mode A Reserved.
Mode B Reserved.
Mode C Instructions are loaded through the HDI08, which is configured to interface with an ISA bus. The HOST ISA
bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying
the address to start loading the program words and then a 24-bit word for each program word to be loaded. The
program words will be stored in contiguous PRAM memory locations starting at the specified starting address.
After reading the program words, program execution starts from the same address where loading started. The
Host Interface bootstrap load program may be stopped by setting the Host Flag 0 (HF0). This will start execution
of the loaded program from the specified starting address.
Mode D As in Mode C, but HDI08 is set for interfacing to Freescale HC11 microcontroller in non-multiplexed mode
Mode E As in Mode C, but HDI08 is set for interfacing to Intel 8051 multiplexed bus
Mode F As in Mode C, but HDI08 is set for interfacing to Freescale 68302 bus.
Table 4-4 Interrupt Priority Level Bits
IPL bits
Interrupts
Enabled
Interrupt
Priority
Level xxL1 xxL0
0 0 No —
0 1 Yes 0
1 0 Yes 1
1 1 Yes 2
Table 4-3 DSP56366 Mode Descriptions