Freescale Semiconductor DSP56366 - Manual (Page 242)

Timer Modes of Operation
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
11-12 Freescale Semiconductor
11.3.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value after the
TE bit in the TCSR is set and a first event occurs. The programmer must initialize the TLR to ensure
correct operation in the appropriate timer operating modes.
• In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter is reloaded each
time after it has reached the value contained by the timer compare register (TCR) and the new event
occurs.
• In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the TCSR is set, the
counter is reloaded with the value in the TLR on each appropriate edge of the input signal.
• In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it has
overflowed and the new event occurs.
• In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it
has reached the value contained by the TCR and the new event occurs. In this mode, the counter is
also reloaded whenever the TLR is written with a new value while the TE bit in the TCSR is set.
• In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as a
free-running counter.
11.3.6 Timer Compare Register (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the counter value. These
two values are compared every timer clock after the TE bit in the TCSR is set. When the values match, the
timer compare flag (TCF) bit is set and an interrupt is generated if interrupts are enabled (if the timer
compare interrupt enable (TCIE) bit in the TCSR is set). The programmer must initialize the TCPR to
ensure correct operation in the appropriate timer operating modes. The TCPR is ignored in measurement
modes.
11.3.7 Timer Count Register (TCR)
The TCR is a 24-bit read-only register. In timer and watchdog modes, the counter’s contents can be read
at any time by reading the TCR register. In measurement modes, the TCR is loaded with the current value
of the counter on the appropriate edge of the input signal, and its value can be read to determine the width,
period, or delay of the leading edge of the input signal. When the timer is in measurement modes, the TIO0
signal is used for the input signal.
11.4 Timer Modes of Operation
Each timer has various operational modes that meet a variety of system requirements. These modes are as
follows:
• Timer
— GPIO, mode 0: Internal timer interrupt generated by the internal clock
— Pulse, mode 1: External timer pulse generated by the internal clock
— Toggle, mode 2: Output timing signal toggled by the internal clock