Freescale Semiconductor DSP56366 - Manual (Page 196)

Operating Modes
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
8-46 Freescale Semiconductor
Data clock and frame sync signals can be generated internally by the DSP or may be obtained from
external sources. If internally generated, the ESAI clock generator is used to derive high frequency clock,
bit clock and frame sync signals from the DSP internal system clock.
8.4.4.3 Frame Sync Selection
The frame sync can be either a bit-long or word-long signal. The transmitter frame format is defined by
the TFSL bit in the TCR register. The receiver frame format is defined by the RFSL bit in the RCR register.
1. In the word-long frame sync format, the frame sync signal is asserted during the entire word data
transfer period. This frame sync length is compatible with Freescale codecs, SPI serial peripherals,
serial A/D and D/A converters, shift registers, and telecommunication PCM serial I/O.
2. In the bit-long frame sync format, the frame sync signal is asserted for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel and National
components, codecs, and telecommunication PCM serial I/O.
The relative timing of the word length frame sync as referred to the data word is specified by the TFSR bit
in the TCR register for the transmitter section, and by the RFSR bit in the RCR register for the receive
section. The word length frame sync may be generated (or expected) with the first bit of the data word, or
with the last bit of the previous word. TFSR and RFSR are ignored when a bit length frame sync is
selected.
Polarity of the frame sync signal may be defined as positive (asserted high) or negative (asserted low). The
TFSP bit in the TCCR register specifies the polarity of the frame sync for the transmitter section. The
RFSP bit in the RCCR register specifies the polarity of the frame sync for the receiver section.
The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is set) only when the
previous frame is completed. If the frame sync goes high before the frame is completed (or before the last
bit of the frame is received in the case of a bit frame sync or a word length frame sync with RFSR set), the
current frame sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent – i.e., a new frame sync does not have to immediately follow the
previous frame. Gaps of arbitrary periods can occur between frames. Enabled transmitters are tri-stated
during these gaps.
When operating in the synchronous mode (SYN=1), all clocks including the frame sync are generated by
the transmitter section.
8.4.4.4 Shift Direction Selection
Some data formats, such as those used by codecs, specify MSB first while other data formats, such as the
AES-EBU digital audio interface, specify LSB first. The MSB/LSB first selection is made by
programming RSHFD bit in the RCR register for the receiver section, and by programming the TSHFD
bit in the TCR register for the transmitter section.
8.4.5 Serial I/O Flags
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in
the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR,