Freescale Semiconductor DSP56366 - Manual (Page 134)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-10 Freescale Semiconductor
When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher
bit-rate transfers are required and the SHI operates in a noise-free environment.
When HFM[1:0] = 10, the narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate
spikes with durations of up to 50ns. This mode is suitable for use in mildly noisy environments and
imposes some limitations on the maximum achievable bit-rate transfer.
When HFM[1:0] = 11, the wide-spike-tolerance filter mode is selected. In this mode the filters eliminate
spikes up to 100 ns. This mode is recommended for use in noisy environments; the bit-rate transfer is
strictly limited. The wide-spike- tolerance filter mode is highly recommended for use in I
2
C bus systems
as it fully conforms to the I
2
C bus specification and improves noise immunity.
NOTE
HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to ‘00’), the
programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting the
HEN bit in the HCSR). Similarly, after changing the HI
2
C bit in the HCSR or the CPOL bit in the HCKR,
while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should
wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR).
7.4.6 SHI Control/Status Register (HCSR)—DSP Side
The HCSR is a 24-bit register that controls the SHI operation and reflects its status. The control bits are
read/write. The status bits are read-only. The bits are described in the following paragraphs. When in the
stop state or during individual reset, the HCSR status bits are reset to their hardware-reset state, while the
control bits are not affected.
7.4.6.1 HCSR Host Enable (HEN)—Bit 0
The read/write control bit HEN, when set, enables the SHI. When HEN is cleared, the SHI is disabled (that
is, it is in the individual reset state, see below). The HCKR and the HCSR control bits are not affected when
HEN is cleared. When operating in master mode, HEN should be cleared only when the SHI is idle
(HBUSY = 0). HEN is cleared during hardware reset and software reset.
Table 7-3 SHI Noise Reduction Filter Mode
HFM1 HFM0 Description
0 0 Bypassed (Disabled)
0 1 Reserved
1 0 Narrow Spike Tolerance
1 1 Wide Spike Tolerance