Freescale Semiconductor DSP56366 - Manual (Page 135)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-11
7.4.6.1.1 SHI Individual Reset
While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins
are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same
state produced by hardware reset or software reset. The individual reset state is entered following a
one-instruction-cycle delay after clearing HEN.
7.4.6.2 HCSR I
2
C/SPI Selection (HI
2
C)—Bit 1
The read/write control bit HI
2
C selects whether the SHI operates in the I
2
C or SPI modes. When HI
2
C is
cleared, the SHI operates in the SPI mode. When HI
2
C is set, the SHI operates in the I
2
C mode. HI
2
C
affects the functionality of the SHI pins as described in Section 2, "Signal/Connection Descriptions" . It is
recommended that an SHI individual reset be generated (HEN cleared) before changing HI
2
C. HI
2
C is
cleared during hardware reset and software reset.
7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2
The read/write control bits HM[1:0] select the size of the data words to be transferred, as shown in
Table 7-4 . HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared
during hardware reset and software reset
.
7.4.6.4 HCSR I
2
C Clock Freeze (HCKFR)—Bit 4
The read/write control bit HCKFR determines the behavior of the SHI when the SHI is unable to service
the master request, when operating in the I
2
C slave mode. The HCKFR bit is used only in the I
2
C slave
mode; it is ignored otherwise.
If HCKFR is set, the SHI holds the clock line to GND if it is not ready to send data to the master during a
read transfer or if the input FIFO is full when the master attempts to execute a write transfer. In this way,
the master may detect that the slave is not ready for the requested transfer, without causing an error
condition in the slave. When HCKFR is set for transmit sessions, the SHI clock generator must be
programmed as if to generate the same serial clock as produced by the external master, otherwise
erroneous operation may result. The programmed frequency should be in the range of 1 to 0.75 times the
external clock frequency.
If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not ready results
in an overrun or underrun error condition.
Table 7-4 SHI Data Size
HM1 HMO Description
0 0 8-bit data
0 1 16-bit data
1 0 24-bit data
1 1 Reserved