Figure 9-4, Esai_1 clock generator functional block diagram -7 – Freescale Semiconductor DSP56366 User Manual

Page 207

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ESAI_1 Programming Model

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor

9-7

Figure 9-4 ESAI_1 Clock Generator Functional Block Diagram

FLAG0 OUT

(SYNC MODE)

FLAG0 IN

(SYNC MODE)

SCKR_1

SCKT_1

RCKD

TCKD

SYN=1

SYN=0

RCLOCK

TCLOCK

INTERNAL BIT CLOCK

SYN=1

RSWS4-RSWS0

TSWS4-TSWS0

RX WORD

LENGTH DIVIDER

TX WORD

LENGTH DIVIDER

RX SHIFT REGISTER

TX SHIFT REGISTER

DIVIDE

BY 2

PRESCALE

DIVIDE BY

1

OR

DIVIDER

DIVIDE BY

1

TO DIVIDE

TPSR

TPM0 - TPM7

RX WORD
CLOCK

TX WORD
CLOCK

SYN=0

DIVIDE

BY 2

PRESCALE

DIVIDE BY

1

OR

DIVIDER

DIVIDE BY

1

TO DIVIDE

F

OSC

RPSR

RPM0 - RPM7

RHCKD=1

DIVIDER

DIVIDE BY

1

TO DIVIDE

RFP0 - RFP3

F

OSC

THCKD=1

DIVIDER

DIVIDE BY

1

TO DIVIDE

TFP0 - TFP3

Notes:
1. F

OSC

is the DSP56300 Core internal clock frequency.

INTERNAL BIT CLOCK

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