Freescale Semiconductor DSP56366 - Manual (Page 164)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
8-14 Freescale Semiconductor
8.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2
TE2 enables the transfer of data from TX2 to the transmit shift register #2. When TE2 is set and a frame
sync is detected, the transmit #2 portion of the ESAI is enabled for that frame. When TE2 is cleared, the
transmitter #2 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX2 when TE2 is cleared but the data is not transferred to the transmit shift
register #2.
The SDO2/SDI3 pin is the data input pin for RX3 if TE2 is cleared and RE3 in the RCR register is set. If
both RE3 and TE2 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE3
and TE2 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE2 and setting it again disables the transmitter #2 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO2/SDI3 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE2 can be left enabled.
8.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3
TE3 enables the transfer of data from TX3 to the transmit shift register #3. When TE3 is set and a frame
sync is detected, the transmit #3 portion of the ESAI is enabled for that frame. When TE3 is cleared, the
transmitter #3 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX3 when TE3 is cleared but the data is not transferred to the transmit shift
register #3.
The SDO3/SDI2 pin is the data input pin for RX2 if TE3 is cleared and RE2 in the RCR register is set. If
both RE2 and TE3 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE2
and TE3 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE3 and setting it again disables the transmitter #3 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO3/SDI2 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE3 can be left enabled.
8.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4
TE4 enables the transfer of data from TX4 to the transmit shift register #4. When TE4 is set and a frame
sync is detected, the transmit #4 portion of the ESAI is enabled for that frame. When TE4 is cleared, the
transmitter #4 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift
register #4.