Freescale Semiconductor DSP56366 - Manual (Page 138)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
7-14 Freescale Semiconductor
transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by hardware reset
and software reset.
NOTE
Clearing HTIE masks a pending transmit interrupt only after a one
instruction cycle delay. If HTIE is cleared in a long interrupt service routine,
it is recommended that at least one other instruction separate the instruction
that clears HTIE and the RTI instruction at the end of the interrupt service
routine.
7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write control bits HRIE[1:0] are used to enable the SHI receive-data interrupts. If HRIE[1:0] are
cleared, receive interrupts are disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits
must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive
interrupts are generated according to
Table 7-6 . HRIE[1:0] are cleared by hardware and software reset.
NOTE
Clearing HRIE[1:0] masks a pending receive interrupt only after a one
instruction cycle delay. If HRIE[1:0] are cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HRIE[1:0] and the RTI instruction at the end of the
interrupt service routine.
7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14
The read-only status bit HTUE indicates whether a transmit-underrun error occurred. Transmit-underrun
errors can occur only when operating in the SPI slave mode or the I
2
C slave mode when HCKFR is cleared.
In a master mode, transmission takes place on demand and no underrun can occur. HTUE is set when both
the shift register and the HTX register are empty and the external master begins reading the next word:
• When operating in the I
2
C mode, HTUE is set in the falling edge of the ACK bit. In this case, the
SHI retransmits the previously transmitted word.
• When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the
assertion of SS if CPHA = 0.
Table 7-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0] Interrupt Condition
00 Disabled Not applicable
01 Receive FIFO not empty
Receive Overrun Error
HRNE = 1 and HROE = 0
HROE = 1
10 Reserved Not applicable
11 Receive FIFO full
Receive Overrun Error
HRFF = 1 and HROE = 0
HROE = 1