Freescale Semiconductor DSP56366 - Manual (Page 245)

Timer Modes of Operation
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 11-15
When the counter value matches the value in the TCPR, the polarity of the TIO0 output signal is inverted.
The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set.
If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received,
and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer
clock.
This process is repeated until the TE bit is cleared, disabling the timer.
The TLR value in the TCPR sets the delay between starting the timer and toggling the TIO0 signal. To
generate output signals with a delay of X clock cycles between toggles, the TLR value should be set to X/2
and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF
bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
11.4.1.4 Timer Event Counter (Mode 3)
In this mode, the timer counts internal events and issues an interrupt when a preset number of events is
counted. Timer 0 can also count external events.
Set the TE bit to clear the counter and enable the timer. The number of events the timer is to count is loaded
into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The
timer clock signal is provided by the prescaler clock output. Timer 0 can be also be clocked from the TIO0
input signal. Each subsequent clock signal increments the counter. If an external clock is used, it must be
internally synchronized to the internal clock and its frequency must be less than the DSP56366 internal
operating frequency divided by 4.
The value of the INV bit in the TCSR determines whether low-to-high (0 to 1) transitions or high-to-low
(1 to 0) transitions increment the counter. If the INV bit is set, high-to-low transitions increment the
counter. If the INV bit is cleared, low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, the TCF bit in the TCSR is set and a compare
interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of
the TLR when the next timer clock is received, and the count is resumed. If TRM bit is cleared, the counter
continues to be incremented on each timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF
bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 TIO0 Clock # KIND NAME
0 0 1 1 Input External 3 Timer Event Counter