Freescale Semiconductor DSP56366 User Manual

Page 337

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Programming Sheets

DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4

Freescale Semiconductor

D-29

Figure D-14. SHI Host Control/Status Register

HBUSY

I

2

C SPI

Mode

0

S

top event

Not Busy

1

S

HI de

tects

Start

SS

detected

(Sl

av

e)

-O

R-

HT

X

/IOSR n

ot

empty (master

)

SHI

*

*

=

Reserved, write as 0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

HRQE

0

HFIF0

H

M1

HM0

H

I

2

CH

E

N

SHI Contr

o

l/St

at

us

X:

$FFF

F91

Rese

t =

$0

0820

0

R

egister (HCSR)

19

18

17

16

23

22

21

20

HRF

F

HROE

HBU

S

Y

*

0

HM

ST

H

T

IE

HBIE

HIDL

E

H

R

Q

E

1

HTDE

HTUE

HRIE

1

HR

IE

0

HRNE

HB

ER

H

E

N

D

escript

ion

0

S

HI disabled

1

S

HI ena

bled

HI

2

C

R

esu

lt

0

SPI mode

1I

2

C mode

HM1

H

M0

Des

criptio

n

0

0

8 bit

dat

a

0

1

16

bit da

ta

1

0

24

bit da

ta

11

R

es

er

ve

d

HFIF

O

D

esc

rip

tio

n

0

1 l

ev

el

FIFO

11

0

le

ve

l

H

M

S

T

Result

0S

la

ve

m

o

de

1M

a

st

er

mode

H

R

QE1

H

RQE0

HREQ

P

in

Operati

o

n

0

0

High impeda

nce

0

1

A

sserted if IOSR rea

dy to

receive new

word

1

0

A

sserted if IOSR rea

dy to

transmit n

ew word

11

I

2

C: Asser

ted if IOSR

ready to tr

ansmit or

receive

S

P

I: Asser

ted if OISR

ready

to

tr

ansm

it and receive

H

ID

L

E

D

escrip

tion

0

B

us busy

1

S

top

even

t

H

B

IE

Des

criptio

n

0

B

us Erro

r Inter

rupt

disable

d

1

B

us Erro

r Inter

rupt en

abled

HTIE

Descrip

tio

n

0

T

ransmit I

nterr

upt disabled

1

T

ransmit I

nterrupt activated

H

o

st Trans

m

it U

n

d

er

ru

n

Error

R

ead Only Status Bit

H

o

st

Trans

fer Dat

a Emp

ty

R

ead Only Status Bit

H

o

st Re

ceive FIF

O

No

t Emp

ty

R

ead Only Status Bit

H

o

st

Receive F

IFO Fu

ll

R

ead Only Status Bit

H

o

st

Receive Overrun

Err

o

r

R

ead Only Status Bit

*

0

HBER

I

2

C SPI

Mode

0

N

o err

or

N

o er

ror

1

N

o acknowledge

SS

asser

ted

HRIE1

HRIE0

Int

errupt

Con

d

it

ion

00

1

0

1

disa

bled

Receive

FIFO not e

m

pty

Receive

Overr

un Err

or

re

se

rv

ed

Rec

ei

ve

FIFO

ful

l

Receive

Overr

un Err

or

n.a.

HR

NE=1 & HROE=0

HR

OE=1

n.a.

HR

FF

=1 & H

R

OE=0

HR

OE=1

0

1

1

*

0

HCK

FR

Application:

Date:

Programmer:

HCKFR

D

esc

ri

ption

0

I2C S

lave

Clock

Free

ze

Disab

led

1

I2C S

lave

Clock

Free

ze

E

nable

d

Sheet 3 of 3

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