2 port d direction register (prrd), Port d direction register (prrd) -13, Figure 10-7 – Freescale Semiconductor DSP56366 User Manual
Page 229: Table 10-6, Dax port gpio control register functionality -13
GPIO (PORT D) - Pins and Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
10-13
10.7.2
Port D Direction Register (PRRD)
The read/write 24-bit Port D Direction Register controls the direction of the DAX GPIO pins. When port
pin[i] is configured as GPIO, PDC[i] controls the port pin direction. When PDC[i] is set, the GPIO port
pin[i] is configured as output. When PDC[i] is cleared the GPIO port pin[i] is configured as input.
Hardware and software reset clear all PRRD bits.
describes the port pin configurations.
Figure 10-7 Port D Direction Register (PRRD)
Table 10-6 DAX Port GPIO Control Register Functionality
PDC1
PC1
ADO/PD1 pin
PDC0
PC0
ACI/PD0 pin
DAX state
0
0
Disconnected
0
0
Disconnected
Personal Reset
0
0
Disconnected
0
1
PD0 Input
Personal Reset
0
0
Disconnected
1
0
PD0 Output
Personal Reset
0
0
Disconnected
1
1
ACI
Enabled
0
1
PD1 Input
0
0
Disconnected
Personal Reset
0
1
PD1 Input
0
1
PD0 Input
Personal Reset
0
1
PD1 Input
1
0
PD0 Output
Personal Reset
0
1
PD1 Input
1
1
ACI
Enabled
1
0
PD1 Output
0
0
Disconnected
Personal Reset
1
0
PD1 Output
0
1
PD0 Input
Personal Reset
1
0
PD1 Output
1
0
PD0 Output
Personal Reset
1
0
PD1 Output
1
1
ACI
Enabled
1
1
ADO
0
0
Disconnected
Enabled
1
1
ADO
0
1
PD0 Input
Enabled
7
PC1
1
PC0
0
4
3
2
5
6
15
12
11
10
13
14
8
9
read as zero, should be written with zero for future compatibility
23
20
19
18
21
22
16
17
PCRD -Port D Control Register - X:$FFFFD7
7
PDC1
1
PDC0
0
4
3
2
5
6
15
12
11
10
13
14
8
9
read as zero, should be written with zero for future compatibility
23
20
19
18
21
22
16
17
PRRD - Port D Direction Register - X:$FFFFD6