Freescale Semiconductor DSP56366 - Manual (Page 120)

HDI08 – External Host Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-26 Freescale Semiconductor
6.6.4 Interrupt Vector Register (IVR)
The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with
MC68000 Family processor vectored interrupts. Only the host processor can read and write this register.
The contents of IVR are placed on the host data bus (H0–H7) when both the HOREQ and HACK signals
are asserted. The contents of this register are initialized to $0F by hardware or software reset, which
corresponds to the uninitialized interrupt vector in the MC68000 Family.
6.6.5 Receive Byte Registers (RXH:RXM:RXL)
The receive byte registers are viewed by the host processor as three 8-bit read-only registers. These
registers are the receive high register (RXH), the receive middle register (RXM) and the receive low
register (RXL). They receive data from the high, middle and low bytes, respectively, of the HOTX register
and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor read
operation.
The memory locations of the receive byte registers are determined by the HLEND bit in the ICR. If the
HLEND bit is set, the RXH is located at address $7, RXM at $6 and RXL at $5. If the HLEND bit is
cleared, the RXH is located at address $5, RXM at $6 and RXL at $7.
When data is transferred from the HOTX register to the receive byte registers, the receive data register full
(RXDF) bit is set. The host processor may program the RREQ bit to assert the external HOREQ/HRRQ
signal when RXDF is set. This indicates that the HDI08 has a full word (either 8, 16 or 24 bits) for the host
processor. When the host reads the receive byte register at host address $7, the RXDF bit is cleared.
6.6.6 Transmit Byte Registers (TXH:TXM:TXL)
The transmit byte registers are viewed as three 8-bit write-only registers by the host processor. These
registers are the transmit high register (TXH), the transmit middle register (TXM) and the transmit low
register (TXL). These registers send data to the high, middle and low bytes, respectively, of the HORX
register and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor
write operation.
If the HLEND bit in the ICR is cleared, the TXH is located at address $5, TXM at $6 and TXL at $7. If
the HLEND bit in the ICR is set, the TXH is located at address $7, TXM at $6 and TXL at $5.
Data may be written into the transmit byte registers when the transmit data register empty (TXDE) bit is
set. The host processor may program the TREQ bit to assert the external HOREQ/HTRQ signal when
TXDE is set. This informs the host processor that the transmit byte registers are empty. Writing to the data
register at host address $7 clears the TXDE bit. The contents of the transmit byte registers are transferred
as 24-bit data to the HORX register when both TXDE and the HRDF bit are cleared. This transfer
operation sets TXDE and HRDF.
7 6 5 4 3 2 1 0
IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0
Figure 6-15 Interrupt Vector Register (IVR)