4 operating modes, 1 esai_1 after reset, 5 gpio - pins and registers – Freescale Semiconductor DSP56366 User Manual
Page 213: 1 port e control register (pcre), Operating modes -13, Esai_1 after reset -13, Gpio - pins and registers -13, Port e control register (pcre) -13, Figure 9-13, Rsma_1 register -13
Operating Modes
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
9-13
9.4
Operating Modes
9.4.1
ESAI_1 After Reset
Hardware or software reset clears the EMUXR register, the port E control register bits and the port E
direction control register bits, which configure all 6 ESAI_1 dedicated I/O pins as disconnected, and all 4
shared pins as belonging to the ESAI. The ESAI_1 is in the individual reset state while all ESAI_1 signals
are programmed as general-purpose I/O or disconnected, and is active only if at least one of the ESAI_1
I/O pins is programmed as belonging to the ESAI_1.
9.5
GPIO - Pins and Registers
The GPIO functionality of the ESAI_1 port is controlled by three registers: Port E Control register
(PCRE), Port E Direction register (PRRE) and Port E Data register (PDRE).
9.5.1
Port E Control Register (PCRE)
The read/write 24-bit Port E Control Register (PCRE) in conjunction with the Port E Direction Register
(PRRE) controls the functionality of the ESAI_1 GPIO pins. Each of the PE(11:0) bits controls the
functionality of the corresponding port pin. See
for the port pin configurations. Hardware and
software reset clear all PCRE bits.
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9B
RS11
RS10
RS9
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-13 RSMA_1 Register
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9C
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-14 RSMB_1 Register