Freescale Semiconductor DSP56366 - Manual (Page 116)

HDI08 – External Host Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-22 Freescale Semiconductor
6.6.1.6 ICR Host Little Endian (HLEND) Bit 5
If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order. If set, the
HDI08 can be accessed by the host in little endian byte order. If the HLEND bit is cleared, the RXH/TXH
register is located at address $5, the RXM/TXM register is located at address $6, and the RXL/TXL
register is located at address $7. If the HLEND bit is set, the RXH/TXH register is located at address $7,
the RXM/TXM register is located at address $6, and the RXL/TXL is located at address $5. See
Table 6-8
for an illustration of the effect of HLEND.
The HLEND function is available only if HDM[2:0]=000 in the host control register (HCR). When
HLEND is available, the ICR bit 6 has no function and should be regarded as reserved.
Bits 6 and 5 function as read/write HM[1:0] bits only when the HCR bits HDM[2:0]=100 (See Table 6-5 ).
The HM0 and HM1 bits select the transfer mode of the HDI08, as shown in Table 6-12 .
When both HM1 and HM0 are cleared, the DMA mode is disabled and the interrupt mode is enabled. In
interrupt mode, the TREQ and RREQ control bits are used for host processor interrupt control via the
external HOREQ output signal, and the HACK input signal is used for the MC68000 Family vectored
interrupt acknowledge input.
When HM1 and/or HM0 are set, they enable the DMA mode and determine the size of the DMA word to
be transferred. In the DMA mode, the HOREQ signal is used to request DMA transfers, the TREQ and
RREQ bits select the direction of DMA transfers (see
Table 6-10 ), and the HACK input signal is used as
a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected
register are enabled onto the host data bus when HACK is asserted. If the DMA direction is from host to
DSP, the selected register is written from the host data bus when HACK is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits, HM0 and HM1. The
HDI08 host side data register selected during a DMA transfer is determined by a 2-bit address counter,
which is preloaded with the value in HM1 and HM0. The address counter substitutes for the HA1 and HA0
host address signals of the HDI08 during a DMA transfer. The host address signal HA2 is forced to one
during each DMA transfer. The address counter can be initialized with the INIT bit feature. After each
DMA transfer on the host data bus, the address counter is incremented to the next data register. When the
address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is
loaded with the value in HM1 and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular
fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 address signals.
For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively,
Table 6-12 Host Mode Bit Definition
HM1 HM0 Mode
0 0 Interrupt Mode (DMA Off)
0 1 DMA Mode (24 Bit)
1 0 DMA Mode (16 Bit)
1 1 DMA Mode (8 Bit)