Freescale Semiconductor DSP56366 User Manual
Page 362
DSP56366 24-Bit Digital Signal Processor, Rev. 4
Index-2
Freescale Semiconductor
DO bit 10
DO loop 6
DRAM 8
DSP56300 core 2
DSP56300 Family Manual i, 2
DSP56303 Technical Data i
E
Enhanced Serial Audio Interface 15, 19
Enhanced Synchronous Audio Interface 1
ESAI 1, 15, 19
ESAI block diagram 1
ESSI0 (GPIO) 1, 2
ESSI1 (GPIO) 1
external address bus 5
external bus control 5, 6, 7
external data bus 5
External Memory Expansion Port 5
F
G
Global Data Bus 6
GPIO 9, 22
GPIO (ESSI0, Port C) 1, 2
GPIO (ESSI1, Port D) 1
GPIO (HI08, Port B) 1
GPIO (Timer) 2
Ground 3
ground 1
H
HA1, HA3-HA6 (HSAR I
2
hardware stack 5
HBER (HCSR Bus Error) 16
HBIE (HCSR Bus Error Interrupt Enable) 13
HBUSY (HCSR Host Busy) 16
HCKR (SHI Clock Control Register) 7
HCSR
Receive Interrupt Enable Bits 14
SHI Control/Status Register 10
HDI08 1, 9, 11, 12
HDM0-HDM5 (HCKR Divider Modulus Select) 9
HEN (HCSR SHI Enable) 10
HFIFO (HCSR FIFO Enable Control) 12
HFM0-HFM1 (HCKR Filter Mode) 9
HI08 9
HI
2
C (HCSR Serial Host Interface I
2
tion) 11
HIDLE (HCSR Idle) 13
HM0-HM1 (HCSR Serial Host Interface Mode) 11
HMST (HCSR Master Mode) 12
Host
Host Interface 9, 1, 9, 11, 12
HREQ Function In SHI Slave Modes 12
HRFF (HCSR Host Receive FIFO Full) 15
HRIE0-HRIE1 (HCSR Receive Interrupt Enable)
14
HRNE (HCSR Host Receive FIFO Not Empty) 15
HROE (HCSR Host Receive Overrun Error) 15
HRQE0-HRQE1 (HCSR Host Request Enable) 12
HTDE (HCSR Host Transmit Data Empty) 15
HTIE (HCSR Transmit Interrupt Enable) 13
HTUE (HCSR Host Transmit Underrun Error) 14
I
I
2
Bit Transfer 17
Bus Protocol For Host Read Cycle 19
Bus Protocol For Host Write Cycle 18
Data Transfer Formats 18
Master Mode 23
Protocol for Host Write Cycle 18
Receive Data In Master Mode 24
Receive Data In Slave Mode 21
Slave Mode 21
Start and Stop Events 17