Freescale Semiconductor DSP56366 - Manual (Page 139)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-15
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector is generated. If a
transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector is generated.
HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware
reset, software reset, SHI individual reset, and during the stop state.
7.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15
The read-only status bit HTDE indicates whether the HTX register is empty and can be written by the DSP.
HTDE is set when the data word is transferred from HTX to the shift register, except in SPI master mode
when CPHA = 0 (see HCKR). When in the SPI master mode with CPHA = 0, HTDE is set after the end
of the data word transmission. HTDE is cleared when the DSP writes the HTX either with write
instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI individual reset, and
during the stop state.
7.4.6.14 HCSR Reserved Bits—Bits 23, 18 and 16
These bits are reserved. They read as zero and should be written with zero for future compatibility.
7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit HRNE indicates that the Host Receive FIFO (HRX) contains at least one data
word. HRNE is set when the FIFO is not empty. HRNE is cleared when HRX is read by the DSP (read
instructions or DMA transfers), reducing the number of words in the FIFO to zero. HRNE is cleared during
hardware reset, software reset, SHI individual reset, and during the stop state.
7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full. HRFF is
cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is
available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset, and during
the stop state.
7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20
The read-only status bit HROE indicates, when set, that a data-receive overrun error has occurred.
Receive-overrun errors cannot occur when operating in the I
2
C master mode, because the clock is
suspended if the receive FIFO is full; nor can they occur in the I
2
C slave mode when HCKFR is set.
HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to the HRX FIFO
and the FIFO is already full (HRFF is set). When a receive-overrun error occurs, the shift register is not
transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun interrupt vector
is generated. If a receive interrupt occurs with HROE cleared, the regular receive-data interrupt vector is
generated.
HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is cleared by
hardware reset, software reset, SHI individual reset, and during the stop state.