Freescale Semiconductor DSP56366 - Manual (Page 177)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-27
8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0
When RE0 is set and TE5 is cleared, the ESAI receiver 0 is enabled and samples data at the SDO5/SDI0
pin. TX5 and RX0 should not be enabled at the same time (RE0=1 and TE5=1). When RE0 is cleared,
receiver 0 is disabled by inhibiting data transfer into RX0. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX0 data register.
If RE0 is set while some of the other receivers are already in operation, the first data word received in RX0
will be invalid and must be discarded.
8.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1
When RE1 is set and TE4 is cleared, the ESAI receiver 1 is enabled and samples data at the SDO4/SDI1
pin. TX4 and RX1 should not be enabled at the same time (RE1=1 and TE4=1). When RE1 is cleared,
receiver 1 is disabled by inhibiting data transfer into RX1. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX1 data register.
If RE1 is set while some of the other receivers are already in operation, the first data word received in RX1
will be invalid and must be discarded.
8.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2
When RE2 is set and TE3 is cleared, the ESAI receiver 2 is enabled and samples data at the SDO3/SDI2
pin. TX3 and RX2 should not be enabled at the same time (RE2=1 and TE3=1). When RE2 is cleared,
receiver 2 is disabled by inhibiting data transfer into RX2. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX2 data register.
If RE2 is set while some of the other receivers are already in operation, the first data word received in RX2
will be invalid and must be discarded.
8.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3
When RE3 is set and TE2 is cleared, the ESAI receiver 3 is enabled and samples data at the SDO2/SDI3
pin. TX2 and RX3 should not be enabled at the same time (RE3=1 and TE2=1). When RE3 is cleared,
receiver 3 is disabled by inhibiting data transfer into RX3. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX3 data register.
If RE3 is set while some of the other receivers are already in operation, the first data word received in RX3
will be invalid and must be discarded.
8.3.4.5 RCR Reserved Bits - Bits 4-5, 17-18
These bits are reserved. They read as zero, and they should be written with zero for future compatibility.
8.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6
The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or
LSB first when RSHFD is set (see
Figure 8-13 and Figure 8-14 ).