Freescale Semiconductor DSP56366 - Manual (Page 183)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-33
the transmit and receive sections. When SYN is set, the synchronous mode is chosen and the transmit and
receive sections use common clock and frame sync signals.
When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section
clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins
SCKR, FSR and HCKR now operate as I/O flags. See
Table 8-7 , Table 8-8 and Table 8-9 for the effects of
SYN on the receiver clock pins.
8.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7
The Transmitter External Buffer Enable (TEBE) bit controls the function of the FSR pin when in the
synchronous mode. If the ESAI is configured for operation in the synchronous mode (SYN=1), and TEBE
is set while FSR pin is configured as an output (RFSD=1), the FSR pin functions as the transmitter external
buffer enable control, to enable the use of an external buffers on the transmitter outputs. If TEBE is cleared
then the FSR pin functions as the serial I/O flag 1. See
Table 8-8 for a summary of the effects of TEBE on
the FSR pin.
8.3.5.7 SAICR Alignment Control (ALC) - Bit 8
The ESAI is designed for 24-bit fractional data, thus shorter data words are left aligned to the MSB (bit
23). Some applications use 16-bit fractional data. In those cases, shorter data words may be left aligned to
bit 15. The Alignment Control (ALC) bit supports these applications.
If ALC is set, transmitted and received words are left aligned to bit 15 in the transmit and receive shift
registers. If ALC is cleared, transmitted and received word are left aligned to bit 23 in the transmit and
receive shift registers.
NOTE
While ALC is set, 20-bit and 24-bit words may not be used, and word length
control should specify 8-, 12- or 16-bit words, otherwise results are
unpredictable.