Freescale Semiconductor DSP56366 - Manual (Page 141)

Characteristics Of The I
2
C Bus
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-17
7.6.1 Overview
The I
2
C bus protocol must conform to the following rules:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in
the data line when the clock line is high are interpreted as control signals (see
Figure 7-7 ).
Figure 7-7 I
2
C Bit Transfer
Accordingly, the I
2
C bus protocol defines the following events:
• Bus not busy —Both data and clock lines remain high.
•
Start data transfer
—The start event is defined as a change in the state of the data line, from high
to low, while the clock is high (see Figure 7-8).
•
Stop data transfer
—The stop event is defined as a change in the state of the data line, from low
to high, while the clock is high (see Figure 7-8).
• Data valid —The state of the data line represents valid data when, after a start event, the data line
is stable for the duration of the high period of the clock signal. The data on the line may be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Figure 7-8 I
2
C Start and Stop Events
Each 8-bit word is followed by one acknowledge bit. This acknowledge bit is a high level put on the bus
by the transmitter when the master device generates an extra acknowledge-related clock pulse. A slave
receiver that is addressed must generate an acknowledge after each byte is received. Also, a master
receiver must generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter. The acknowledging device must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge-related clock pulse (see
Figure 7-9 ).
SDA
SCL
Data Line
Stable:
Data Valid
Change
of Data
Allowed AA0422
S P
Start Event Stop Event
SDA
SCL
AA0423