Freescale Semiconductor DSP56366 - Manual (Page 155)

ESAI Data and Control Pins
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-5
When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR
register. When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR
register, and the data in the OF0 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When this pin is configured as the input flag IF0, the data value at the
pin is stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the
slot in network mode.
SCKR may be programmed as a general-purpose I/O pin (PC0) when the ESAI SCKR function is not being
used.
NOTE
Although the external ESAI serial clock can be independent of and
asynchronous to the DSP system clock, the DSP clock frequency must be at
least three times the external ESAI serial clock frequency and each ESAI
serial clock phase must exceed the minimum of 1.5 DSP clock periods.
For more information on pin mode and definition, see Table 8-7 and on receiver clock signals see
Table 8-1 .
8.2.8 Transmitter Serial Clock (SCKT)
SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface. The direction
of this pin is determined by the TCKD bit in the TCCR register. The SCKT is a clock input or output used
by all the enabled transmitters in the asynchronous mode (SYN=0) or by all the enabled transmitters and
receivers in the synchronous mode (SYN=1) (see
Table 8-2 ).
Table 8-1 Receiver Clock Sources (asynchronous mode only)
RHCKD RFSD RCKD
Receiver
Bit Clock
Source
OUTPUTS
0 0 0 SCKR
0 0 1 HCKR SCKR
0 1 0 SCKR FSR
0 1 1 HCKR FSR SCKR
1 0 0 SCKR HCKR
1 0 1 INT HCKR SCKR
1 1 0 SCKR HCKR FSR
1 1 1 INT HCKR FSR SCKR