Freescale Semiconductor DSP56366 - Manual (Page 38)

Clock and PLL
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
2-4 Freescale Semiconductor
2.4 Clock and PLL
GND
A
(4) Address Bus Ground — GND
A
is an isolated ground for sections of the address bus I/O drivers. This
connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are four GND
A
connections.
GND
D
(4) Data Bus Ground — GND
D
is an isolated ground for sections of the data bus I/O drivers. This
connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are four GND
D
connections.
GND
C
(2) Bus Control Ground — GND
C
is an isolated ground for the bus control I/O drivers. This connection
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GND
C
connections.
GND
H
Host Ground — GND
h
is an isolated ground for the HD08 I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There is one GND
H
connection.
GND
S
(2) SHI, ESAI, ESAI_1, DAX and Timer Ground — GND
S
is an isolated ground for the SHI, ESAI, ESAI_1,
DAX and Timer. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There are two GND
S
connections.
Table 2-4 Clock and PLL Signals
Signal
Name
Type
State during
Reset
Signal Description
EXTAL Input Input External Clock Input — An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5 V.
PCAP Input Input PLL Capacitor — PCAP is an input connecting an off-chip capacitor to the PLL
filter. Connect one capacitor terminal to PCAP and the other terminal to V
CCP
.
If the PLL is not used, PCAP may be tied to V
CC
, GND, or left floating.
PINIT/NMI Input Input PLL Initial/Nonmaskable Interrupt — During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input
is a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
This input cannot tolerate 5 V.
Table 2-3 Grounds (continued)
Ground Name Description