Freescale Semiconductor DSP56366 - Manual (Page 118)

HDI08 – External Host Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-24 Freescale Semiconductor
The host processor can select the starting address of any of the 128 possible interrupt routines in the DSP
by writing the interrupt routine address divided by 2 into the HV bits. The host processor can thus force
execution of any of the existing interrupt handlers (IRQA, IRQB, etc.) and can use any of the reserved or
otherwise unused addresses provided they have been pre-programmed in the DSP. HV[6:0] is set to $32
(vector location $0064) by hardware, software, individual and stop resets.
6.6.2.2 CVR Host Command Bit (HC) Bit 7
The HC bit is used by the host processor to handshake the execution of host command interrupts.
Normally, the host processor sets HC to request the host command interrupt from the DSP core. When the
host command interrupt is acknowledged by the DSP core, the HC bit is cleared by the HDI08 hardware.
The host processor can read the state of HC to determine when the host command has been accepted. After
setting HC, the host must not write to the CVR again until HC is cleared by the HDI08 hardware. Setting
HC causes the host command pending (HCP) in the HSR to be set. The host can write to the HC and HV
bits in the same write cycle.
6.6.3 Interface Status Register (ISR)
The ISR is an 8-bit read-only status register used by the host processor to interrogate the status and flags
of the HDI08. The host processor can write to this address without affecting the internal state of the HDI08,
which is useful if the user desires to access all of the HDI08 registers by stepping through the HDI08
addresses. The ISR cannot be accessed by the DSP core. The ISR bits are described in the following
paragraphs.
6.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0
The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP core
and may be read by the host processor. RXDF is set when the contents of HOTX is transferred to the
receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to HLEND bit)
register is read by the host processor. RXDF can be cleared by the host processor using the initialize
function. RXDF may be used to assert the external HOREQ signal if the RREQ bit is set. Regardless of
whether the RXDF interrupt is enabled, RXDF indicates whether the RX registers are full and data can be
latched out (so that polling techniques may be used by the host processor).
6.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1
The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and can be written
by the host processor. TXDE is set when the contents of the transmit byte registers are transferred to the
HORX register. TXDE is cleared when the transmit (TXL or TXH according to HLEND bit) register is
7 6 5 4 3 2 1 0
HREQ HF3 HF2 TRDY TXDE RXDF
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-14 Interface Status Register (ISR)