Freescale Semiconductor DSP56366 - Manual (Page 112)

HDI08 – External Host Programmer’s Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
6-18 Freescale Semiconductor
Figure 6-11 HSR-HCR Operation
6.6 HDI08 – External Host Programmer’s Model
The HDI08 has been designed to provide a simple, high speed interface to a host processor. To the host
bus, the HDI08 appears to be eight byte-wide registers. Separate transmit and receive data registers are
double-buffered to allow the DSP core and host processor to transfer data efficiently at high speed. The
host may access the HDI08 asynchronously by using polling techniques or interrupt-based techniques.
The HDI08 appears to the host processor as a memory-mapped peripheral occupying 8 bytes in the host
processor address space (See
Table 6-8 ). The eight HDI08 include the following:
• A control register (ICR)
• A status register (ISR)
• Three data registers (RXH/TXH, RXM/TXM and RXL/TXL)
• Two vector registers (IVR and CVR)
These registers can be accessed only by the host processor.
Host processors may use standard host processor instructions (e.g., byte move) and addressing modes to
communicate with the HDI08 registers. The HDI08 registers are aligned so that 8-bit host processors can
use 8/16/24-bit load and store instructions for data transfers. The HOREQ/HTRQ and HACK/HRRQ
handshake flags are provided for polled or interrupt-driven data transfers with the host processor. Because
the DSP interrupt response, most host microprocessors can load or store data at their maximum
programmed I/O instruction rate without testing the handshake flags for each transfer. If full handshake is
not needed, the host processor can treat the DSP as a fast device, and data can be transferred between the
host processor and the DSP at the fastest host processor data rate.
15 0
HF3 HF2 HCIE HTIE HRIE
ENABLE
HCR
HF1 HF0 HCP HTDE HRDF
15 0
X:HSR
X:HCR
DSP CORE INTERRUPTS
RECIEVE DATA FULL
TRANSMIT DATA EMPTY
HOST COMMAND
HSR
STATUS