Freescale Semiconductor DSP56366 - Manual (Page 149)

SHI Programming Considerations
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-25
7.7.5 SHI Operation During DSP Stop
The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active.
While the DSP is in the stop state, the SHI remains in the individual reset state.
While in the individual reset state the following is true:
• If the SHI was operating in the I
2
C mode, the SHI signals are disabled (high impedance state).
• If the SHI was operating in the SPI mode, the SHI signals are not affected.
• The HCSR status bits and the transmit/receive paths are reset to the same state produced by
hardware reset or software reset.
• The HCSR and HCKR control bits are not affected.
NOTE
It is recommended that the SHI be disabled before entering the stop state.