Freescale Semiconductor DSP56366 - Manual (Page 365)

DSP56366 24-Bit Digital Signal Processor, Rev. 4
Freescale Semiconductor Index-5
TC0–TC3 bits 7
TCF 11
TCIE bit 7
TCPR 12
TCR 12
TCSR register 6
bit 0—Timer Enable bit (TE) 6
bit 2—Timer Compare Interrupt Enable bit
(TCIE) 7
bits 4–7—Timer Control bits (TC0–TC3) 7
bit 13—Data Output bit (DO) 10
reserved bits—bits 3, 10, 14, 16–19, 22, 23 11
TE bit 6
Test Access Port (TAP) 7
Timer 1, 22
timer
special cases 20
Timer (GPIO) 2
Timer Compare Interrupt Enable bit (TCIE) 7
Timer Control bits (TC0–TC3) 7
Timer Control/Status Register (TCSR) 6
Timer Enable bit (TE) 6
timer mode
mode 0—GPIO 13
mode 1—timer pulse 14
mode 2—timer toggle 14
mode 3—timer event counter 15
mode 4—measurement input width 16
mode 5—measurement input period 17
mode 6—measurement capture 17
mode 7—pulse width modulation 18
mode 8—reserved 19
mode 9—watchdog pulse 19, 20
modes 11–15—reserved 20
Timer module
architecture 1
Timer Prescaler Count Register (TPCR) 6
Timer Prescaler Load Register (TPLR) 5
TLR 12
TOF 11
TOIE 7
TPCR register 6
bits 0-20—Prescaler Counter Value bits
(PC0-PC20) 6
bit 21-23—reserved bits 6
reserved bits—bits 21-23 6
TPLR register 5
bits 0-20—Prescaler Load Value bits
(PL0-PL20) 5
bits 21-22—Prescaler Source bits (PL0-PL20)
5
bit 23—reserved bit 6
reserved bit—bit 23 6
Transmitter High Frequency Clock Divider 11
TRM 10
V
VBA register 6
Vector Base Address register (VBA) 6
X
X Memory Address Bus (XAB) 6
X Memory Data Bus (XDB) 6
X Memory Expansion Bus 6
XAB 6
XDB 6
Y
Y Memory Address Bus (YAB) 6
Y Memory Data Bus (YDB) 6
Y Memory Expansion Bus 6
YAB 6
YDB 6