Freescale Semiconductor DSP56366 - Manual (Page 171)

ESAI Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 8-21
8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16
TFSR determines the relative timing of the transmit frame sync signal as referred to the serial data lines,
for a word length frame sync only (TFSL=0). When TFSR is cleared the word length frame sync occurs
together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync
starts one serial clock cycle earlier (i.e together with the last bit of the previous data word).
8.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17
When PADC is cleared, zero padding is disabled. When PADC is set, zero padding is enabled. PADC, in
conjunction with the TWA control bit, determines the way that padding is done for operating modes where
the word length is less than the slot length. See the TWA bit description in
Section 8.3.2.8, "TCR Transmit
Word Alignment Control (TWA) - Bit 7" for more details.
Since the data word is shorter than the slot length, the data word is extended until achieving the slot length,
according to the following rules:
1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data
bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1),
zeroes are transmitted after the data word has been transmitted.
2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), then the first
data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1),
zeroes are transmitted before the transmission of the data word.
8.3.2.14 TCR Reserved Bit - Bits 18
This bit is reserved. It reads as zero, and it should be written with zero for future compatibility.
8.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19
The TPR control bit is used to put the transmitter section of the ESAI in the personal reset state. The
receiver section is not affected. When TPR is cleared, the transmitter section may operate normally. When
TPR is set, the transmitter section enters the personal reset state immediately. When in the personal reset
state, the status bits are reset to the same state as after hardware reset. The control bits are not affected by
the personal reset state. The transmitter data pins are tri-stated while in the personal reset state; if a stable
logic level is desired, the transmitter data pins should be defined as GPIO outputs, or external pull-up or
pull-down resistors should be used. The transmitter clock outputs drive zeroes while in the personal reset
state. Note that to leave the personal reset state by clearing TPR, the procedure described in
Section 8.6,
"ESAI Initialization Examples" should be followed.
8.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20
When TEIE is set, the DSP is interrupted when both TDE and TUE in the SAISR status register are set.
When TEIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by writing to
all the data registers of the enabled transmitters clears TUE, thus clearing the pending interrupt.