Freescale Semiconductor DSP56366 - Manual (Page 222)

DAX Internal Architecture
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
10-6 Freescale Semiconductor
10.5.4.2 DAX Channel A User Data (XUA)—Bit 11
The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the channel A subframe in the next
frame.
10.5.4.3 DAX Channel A Channel Status (XCA)—Bit 12
The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the channel A subframe in the next
frame.
10.5.4.4 DAX Channel B Validity (XVB)—Bit 13
The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the channel B subframe in the
next frame.
10.5.4.5 DAX Channel B User Data (XUB)—Bit 14
The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the channel B subframe in the next
frame.
10.5.4.6 DAX Channel B Channel Status (XCB)—Bit 15
The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the channel B subframe in the next
frame.
10.5.4.7 XNADR Reserved Bits—Bits 0-9, 16–23
These XNADR bits are reserved. They read as 0, and should be written with 0 to ensure compatibility with
future device versions.
10.5.5 DAX Non-Audio Data Buffer (XNADBUF)
The XNADBUF is a 3-bit register that temporarily holds channel B non-audio data (XVB, XUB and XCB)
for the current transmission while the channel A data is being transmitted. This mechanism provides
programmers more instruction cycles to store the next frame’s non-audio data to the XCB, XUB, XVB,
XCA, XUA and XVA bits in the XNADR. The data in the XNADBUF register is transferred to the
XADSR along with the contents of the XADBUF register at the beginning of channel B transmission.
NOTE
The XNADBUF register is not directly accessible by DSP instructions.
10.5.6 DAX Control Register (XCTR)
The XCTR is a 24-bit read/write register that controls the DAX operation. The contents of the XCTR are
shown in
Figure 10-2 . XCTR is cleared by software reset and hardware reset. The XCTR bits are described
in the following paragraphs.