Freescale Semiconductor DSP56366 - Manual (Page 137)

Serial Host Interface Programming Model
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor 7-13
7.4.6.8 HCSR Idle (HIDLE)—Bit 9
The read/write control/status bit HIDLE is used only in the I
2
C master mode; it is ignored otherwise. It is
only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing to HTX. To
ensure correct transmission of the slave device address byte, HIDLE should be set only when HTX is
empty (HTDE = 1). After HIDLE is set, a write to HTX clears HIDLE and causes the generation of a stop
event, a start event, and then the transmission of the eight MSBs of the data as the slave device address
byte. While HIDLE is cleared, data written to HTX is transmitted as is. If the SHI completes transmitting
a word and there is no new data in HTX, the clock is suspended after sampling ACK. If HIDLE is set when
the SHI completes transmitting a word with no new data in HTX, a stop event is generated.
HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If HIDLE is
cleared, the reception is acknowledged by sending a 0 bit on the SDA line at the ACK clock tick. If HIDLE
is set, the reception is not acknowledged (a 1 bit is sent). It is used to signal an end-of-data to a slave
transmitter by not generating an ACK on the last byte. As a result, the slave transmitter must release the
SDA line to allow the master to generate the stop event. If the SHI completes receiving a word and the
HRX FIFO is full, the clock is suspended before transmitting an ACK. While HIDLE is cleared the bus is
busy, that is, the start event was sent but no stop event was generated. Setting HIDLE causes a stop event
after receiving the current word.
HIDLE is set while the SHI is not in the I
2
C master mode, while the chip is in the stop state, and during
hardware reset, software reset and individual reset.
NOTE
Programmers should take care to ensure that all DMA channel service to
HTX is disabled before setting HIDLE.
7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
The read/write control bit HBIE is used to enable the SHI bus-error interrupt. If HBIE is cleared, bus-error
interrupts are disabled, and the HBER status bit must be polled to determine if an SHI bus error occurred.
If both HBIE and HBER are set, the SHI requests an SHI bus-error interrupt service from the interrupt
controller. HBIE is cleared by hardware reset and software reset.
NOTE
Clearing HBIE masks a pending bus-error interrupt only after a one
instruction cycle delay. If HBIE is cleared in a long interrupt service routine,
it is recommended that at least one other instruction separate the instruction
that clears HBIE and the RTI instruction at the end of the interrupt service
routine.
7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
The read/write control bit HTIE is used to enable the SHI transmit data interrupts. If HTIE is cleared,
transmit interrupts are disabled, and the HTDE status bit must be polled to determine if HTX is empty. If
both HTIE and HTDE are set and HTUE is cleared, the SHI requests an SHI transmit-data interrupt service
from the interrupt controller. If both HTIE and HTUE are set, the SHI requests an SHI